library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom is
port(
     addr:in std_logic_vector(3 downto 0);
     en:in std_logic;
     data:out std_logic_vector(7 downto 0));
end;
architecture one of rom is
type memory is array(0 to 15)of std_logic_vector(7 downto 0);
signal data1:memory:=("00000001","00000010","00000001","00000001",
"00000001","00000001","00000001","00000001",
"00000001","00000001","00000001","00000001",
"00000001","00000001","00000001","00000001");
signal addr1:integer range 0 to 15;
begin
  addr1<=conv_integer(addr);
  process(en,addr1,addr,data1)
  begin
   if en='0' then
     data<=data1(addr1);
   else
     data<=(others=>'Z');
   end if;
  end process;
end;